Open source

AURIG

An open-source FPGA tooling stack for on-premise labs. Five tools, each useful on its own, sharing one project manifest. Apache-2.0, developed and maintained by LogiMentor.

How the pieces fit

AURIG Core sits at the bottom: a VHDL parser and the canonical project manifest. AURIG Lint and AURIG Doc are built directly on it, reading the same parsed structure to check code and to document it; both need a Core checkout to run.

AURIG Build is independent. It drives an FPGA project from the same manifest schema through synthesis, implementation, and bitstream across four vendors, and it can be used on its own with no other part of the stack installed.

AURIG Sentinel sits on top as the scheduler. It runs pipelines unattended on the workstation that holds the EDA licences, delegating the HDL-aware work outward rather than doing it itself.

The five tools

What you can try without a licence

Linting and documentation need no vendor toolchain and no licence, and simulation-based regression can run on GHDL. Synthesis, implementation, and bitstream generation need the corresponding vendor tools installed.

Status

Early access. Published and usable, with the interfaces still free to change. Each repository is the current source of truth for what its release supports.

Getting started

AURIG Build and AURIG Sentinel install from PyPI. Core, Lint, and Doc are Tcl packages used from a checkout. Each repository carries its own installation and usage documentation.

← Open source