An on-premise pipeline orchestrator for FPGA teams: per-project YAML, scheduled unattended runs, logs and artifacts bundled per run.
AURIG Sentinel schedules and runs FPGA project pipelines on the workstation that owns the licensed toolchain. Each project is described by a YAML file. Sentinel validates them, fetches the current code, runs the phases you have enabled, captures the logs, and writes a timestamped run directory with the artifacts bundled for you. A configurable time window keeps the machine free during the day and lets the run fire overnight.
Sentinel is deliberately narrow, and it is not a replacement for a CI system. It is pull-based on a timer rather than driven by webhooks, so it does not gate pull requests. It has no web interface, no user management, and no distributed scheduling. What it does instead is run reliably on a single machine, close to the tools and the silicon.
That trade is aimed at a specific situation: toolchains that are licensed and node-locked and cannot move to cloud runners, designs and IP that must not leave the lab network, and small teams without a dedicated CI administrator who would rather keep their pipeline definition in version control than in a web UI.
Sentinel does not parse VHDL and does not own your project structure. The HDL-aware work and the vendor builds are delegated outward, to the other AURIG tools and to scripts your own project provides. The phases available in the current release are listed in the repository.