The shared Tcl foundation of the AURIG stack: a VHDL parser that turns source into a queryable dictionary, plus project utilities and the canonical manifest schema.
AURIG Core is the layer the rest of the AURIG tools are built on. Its parser reads a VHDL file into a structured dictionary, and a family of query helpers reads that structure back out: entity names, ports, generics, libraries, use clauses, architectures, instantiations, signals, and packages, without traversing the dictionary by hand.
Alongside the parser it provides the practical utilities a VHDL tool needs. It reads and writes YAML and INI, converts between them, resolves paths, and expands a project manifest's file set patterns into a concrete list of source files. It also owns the canonical AURIG project manifest schema, with normalize and validate checked against a JSON Schema kept in the repository.
Its own validator is deliberately lenient, accepting anything a valid manifest could reasonably be; AURIG Build is the strict, authoritative validator for the same schema.
Core is the common dependency of AURIG Lint and AURIG Doc, and it is rarely the tool you reach for directly. It is worth knowing about for a different reason: if you are writing your own VHDL tooling, this is the layer to build on rather than writing another parser. It is a fully standalone package, and the parser itself needs no external Tcl libraries.