Generates browsable documentation from VHDL, for a single file or a whole project, as Markdown or self-contained HTML.
AURIG Doc turns VHDL sources into documentation you can read and share. Point it at one file to produce a Markdown or self-contained HTML page, or at a project manifest to document the whole design, which emits a page per entity and package plus a navigable index.
It parses sources with the AURIG Core VHDL parser rather than bundling a parser of its own, so the structure it documents is the same structure the rest of the stack sees.
Running it needs Tcl and a checkout of AURIG Core on the Tcl package path. The single-file path needs nothing else. Documenting a whole project from a YAML manifest additionally needs tcllib. No vendor toolchain and no licence are required.