FPGA project automation: one YAML file drives synthesis, implementation, bitstream, and simulation across Vivado, Quartus, Diamond, and Radiant.
AURIG Build runs an FPGA project from a single YAML file. Project metadata, file sets, target device, and constraints live in one place, and the same command line drives creating the vendor project, synthesis, implementation, and bitstream generation. Hardware export is available on Vivado. Simulation runs through VUnit, Questa, or XSim.
Four synthesis backends are supported: Xilinx Vivado, Intel Quartus, Lattice Diamond, and Lattice Radiant. The tool sources the vendor environment scripts and checks the installed tool version before it runs, so a misconfigured workstation fails early rather than halfway through a build.
Paths that differ from machine to machine do not have to pollute the shared configuration. A per-machine overlay file, kept out of version control, is merged on top of the committed one.
You do not have to start from scratch to try it. It can import an existing Vivado, Quartus, or Diamond project and generate the layout and configuration for you.
It is a standalone Python package, installable from PyPI, and does not depend on the rest of the stack. It shares the canonical AURIG project manifest with AURIG Core and is the authoritative strict validator for that schema.
Some limits are worth knowing before you invest. Diamond support is marked experimental, since the synthesis engine choice is not yet configurable from the YAML. Radiant synthesis is supported but there is no Radiant importer. Using any backend requires that vendor's toolchain installed locally.