Vendor-independent VHDL utility library — counters, delays, CDC, CRC, arbiters, and sizing helpers, hardened across 20 years of real FPGA designs.
lm_util is the foundational VHDL utility library used across LogiMentor FPGA designs — the "Swiss-army knife" of reusable blocks you'd otherwise rebuild from scratch on each new project.
It collects the building blocks every FPGA project needs: a package of helper functions (ceil_log2 for bus sizing, direct conversion helpers over numeric_std) plus synthesizable modules — counters and watchdogs, fixed and variable delay lines, SRL-style shift registers, clock-domain-crossing synchronizers, parallel and serial CRC engines, edge detectors, encoders, multiplexers, and priority/round-robin arbiters.
There's no exotic claim here: most teams build a utility library like this sooner or later. The difference is that this one is vendor-independent (standard IEEE libraries, no vendor primitives), verified with self-checking VUnit testbenches under CI, and hardened across two decades of shipped designs. If you're starting to structure your own internal VHDL libraries and want a field-proven base instead of rebuilding these pieces again, that's what lm_util is for.