Floating-point arithmetic for FPGA in VHDL, using IEEE-754 field conventions — vendor-independent RTL you can inspect, verify, and carry across FPGA families.
lm_math_float is a VHDL RTL library of floating-point arithmetic for FPGA designs — for the cases where fixed-point isn't the right trade-off and vendor floating-point IP isn't a good fit.
Most DSP fits in fixed-point, but some designs genuinely need floating-point: feedback systems where errors propagate and dynamic range matters — PID controllers, IIR filters, and similar control or filtering paths. It also matters in safety-critical work, where closed vendor soft-IP can be hard to justify because the arithmetic source has to be inspectable, reviewable, and verifiable. That's where an open, vendor-independent VHDL implementation earns its place — you can read it, verify it against your own tests, and carry it across FPGA families.
It provides add/subtract, multiply, divide, square root, complex product, and fixed-/floating-point conversions, with parametric exponent and mantissa widths and four selectable rounding modes. Note that the default round-to-nearest breaks ties upward, not the IEEE-754 round-to-nearest-even rule — so it uses IEEE-754 field conventions without claiming full IEEE-754 compliance.