Fixed-point arithmetic for FPGA — a synthesizable VHDL building block for DSP and math datapaths, with a Python reference model verified bit-for-bit against fxpmath.
lm_math_fi provides fixed-point arithmetic for FPGA designs — a synthesizable VHDL base for signal-processing and math datapaths. It's the arithmetic layer LogiMentor uses under its own DSP modules.
Fixed-point hardware is about control: instead of wiring the vendor's DSP primitives directly, you work from vendor-independent arithmetic you fully understand and can verify. lm_math_fi pairs the synthesizable VHDL with a Python reference model checked bit-for-bit against fxpmath, so you can build a bit-accurate golden model, run error analysis, and validate your RTL against a trusted software reference rather than hoping the hardware matches your intent.
There's no exotic claim here: fixed-point math is something many FPGA teams eventually build. The value is a verified base you can rely on — more portable across FPGA families than hand-wiring vendor DSP blocks, and already the foundation for LogiMentor's signal-processing modules.